Download Advanced ASIC Chip Synthesis Using Synopsys Tools by Himanshu Bhatnagar PDF
By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® Design Compiler® actual Compiler® and PrimeTime®, Second Edition describes the complicated options and methods used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the full ASIC layout circulation method distinctive for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this ebook is on real-time software of Synopsys instruments, used to strive against quite a few difficulties obvious at VDSM geometries. Readers can be uncovered to an efficient layout method for dealing with complicated, sub-micron ASIC designs. importance is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to format, actual synthesis, and static timing research. At each one step, difficulties comparable to every part of the layout circulate are pointed out, with recommendations and work-around defined intimately. moreover, the most important concerns comparable to structure, which include clock tree synthesis and back-end integration (links to structure) also are mentioned at size. additionally, the ebook includes in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding types, specified in the direction of optimum synthesis answer.
objective audiences for this publication are working towards ASIC layout engineers and masters point scholars venture complex VLSI classes on ASIC chip layout and DFT options.
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Additional info for Advanced ASIC Chip Synthesis Using Synopsys Tools
The clock tree insertion is optional and depends solely on the design and user’s preference. Users may opt to use more traditional methods of routing the clock network, for example, using fishbone/spine structure for the clocks in order to reduce the total delay and skew of the clock. As technologies shrink, the spine approach is getting more difficult to implement due to the increase in resistance (thus, RC delays) of the interconnect wires. It is therefore the intent of this section (and the entire book) to stress solely on the clock tree synthesis approach.
Furthermore, all output signals must be delayed by 10ns with respect to the clock. 25 micron. In order to achieve greater accuracy due of variance in process, two Synopsys standard cell technology libraries, characterized for worst-case and the best-case process parameters are used. sdb. db library is BEST. It is assumed that the functionality of the design has been verified by dynamically simulating it at the RTL level. , map the design to the gates belonging to the specified technology library.
Db library. sv The above script contains a user-defined variable called active_design that defines the name of the module to be synthesized. This variable is used throughout the script, thus making the rest of the script generic. By redefining the value of active_design to other sub-modules (tap_instruction and tap_state), the same script may be used to synthesize the sub-modules. Users can apply the same concept to clock names, clock periods, etc. in order to parameterize the scripts. Lets assume that you have successfully synthesized three sub-blocks, namely tap_bypass, tap_instruction and tap_state.